Sofics technology has been applied for many different applications. Some applications need I/O circuits and ESD protection that can tolerate a higher voltage.
ICs manufactured on advanced nodes like FinFET processes only support I/Os up to 1.8V. However, for communication with legacy chips higher voltages are required like 3.3V or even 5V.
Another reason for higher voltage tolerance comes from the requirement to power the chips from USB or batteries at 4.5V – 5V.
Sometimes system makers demand high EOS and surge tolerance voltages, beyond the GPIO capabilities.
Sofics has delivered unique ESD protection clamps for many projects when the customer designed the functional I/O circuit. More recently, Sofics has also designed several functional I/O circuits with higher voltage capabilities.
Contact us (info@sofics.com) to discuss your application.
We can ensure your interface can tolerate a higher voltage.
Examples in different processes
Examples for ESD protection clamps on different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.
Cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.
Mature CMOS (0.5um to 180nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 180nm | 5V rail | > 8 kV HBM | < 5 nA |
| TSMC 180nm | 5V I/O | > 8 kV HBM | < 5 nA |
| TSMC 180nm | 7V I/O | > 2 kV HBM | < 50 nA |
| TowerSemi 350nm | 4.5V rail | > 8 kV HBM | < 100 nA |
Mainstream CMOS (130nm to 65 nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 130nm | 5V rail | > 3 kV HBM | < 1 nA |
| TSMC 130nm | 5V I/O | > 3 kV HBM | < 1 nA |
| TSMC 130nm | 7V I/O | > 4 kV HBM | < 1 nA |
| TSMC 65nm | 5V I/O OVT | > 4 kV HBM | < 1 nA |
| TSMC 65nm | 5V I/O | > 4 kV HBM | < 100 nA |
Advanced CMOS (40 to 22nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 40nm | 5V rail | > 2 kV HBM | < 10 nA |
| TSMC 40nm | 5V I/O | > 2 kV HBM | < 10 nA |
| TSMC 28nm | 3.9V I/O | > 2 kV HBM | < 50 nA |
| TSMC 28nm | 5.5V I/O | > 2 kV HBM | < 400 nA |
| TSMC 28nm | 6.5V I/O | > 2 kV HBM | < 400 nA |
| TSMC 28nm | 12V I/O | > 2 kV HBM | < 40 nA |
| UMC 28nm | 8.6V I/O | > 200 V HBM | < 1 uA |
Example I/O circuit: 3.3V Capable GPIO on TSMC 28nm RF HPC+: A 3.3V general purpose I/O that is built using thick-gate, 1.98V MOS devices. Supported features include core isolation, output enable and pull enable (datasheet).
Example I/O circuit: 1.2V Capable GPIO on TSMC 28nm RF HPC+: A 1.2V general purpose I/O that is built using thin-gate, 0.9V core MOS devices. Supported features include core isolation, programmable slew rate compensation, programmable drive strength, input/output enable, pull select and pull enable. The GPIO targets radiation hard applications prohibiting the use of thick gate I/O devices (Datasheet).
FinFET technology
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 16nm | 5V rail | > 1 kV HBM | < 30 nA |
| TSMC 16nm | 5V I/O | > 1 kV HBM | < 30 nA |
| TSMC 12nm | 3.3V rail | > 3 kV HBM | < 60 nA |
| TSMC 12nm | 5V I/O | > 4 kV HBM | < 3 uA |
| TSMC 7nm | 3.3V rail | > 2 kV HBM | < 1.5 uA |
| TSMC 7nm | 3.3V I/O | > 2 kV HBM | 5 nA |
| TSMC 5nm | 1.8V rail | > 1 kV HBM | < 500 pA |
| TSMC 5nm | 2.5V I/O | > 2 kV HBM | 20 nA |
| TSMC 5nm | 3.3V I/O | > 3 kV HBM | 20 nA |
| Samsung Foundry 4nm | 3.3V rail | > 7 kV HBM | 5 nA |
| Samsung Foundry 4nm | 3.3V I/O | > 5 kV HBM | 150 pA |
| TSMC 3nm | 3.3V I/O | > 2 kV HBM | 10 nA |
Example I/O circuit: 1.8V Capable GPIO on Samsung Foundry 4nm FinFET: A 1.8V general purpose I/O that is built using 1.2V MOS FINFET devices. Supported features include core isolation, output enable and pull enable (datasheet).
FinFET technology
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 2nm | 1.8V rail | > 6 kV HBM | < 17 nA |
| TSMC 2nm | 1.8V I/O | > 6 kV HBM | < 150 nA |
SOI technology
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| GF 22FDX | 3.3V rail | > 5 kV HBM | < 10 pA |
| GF 22FDX | 3.3V I/O | > 2 kV HBM | < 500 pA |
| GF 22FDX | 5V rail | > 4 kV HBM | < 10 nA |
These are examples from many IP delivery projects. If you did not find the example you were looking for you should contact us (info@sofics.com) to discuss your application and requirements.
Our solutions can support a higher voltage.
Testimonial: Nvidia – Icera
- Icera 410 LTE multimode data modem
- TSMC 40nm and 28nm
- Overvoltage tolerance
Pete Hughes, Vice President, Mobile
“A solution that works at high voltages and provides good protection. This enables us to handle off-chip interfaces of up to 3.6 volts, even for non-standard multimedia interfaces”
Testimonial: eSilicon design service
- 15V interfaces
- Solar-panel power converters. DC – AC conversion
- 180nm LDMOS
Hugh Durdan, eSilicon COO
“We needed to protect a 15V interface on a 0.18um high-voltage LDMOS chip that we produce for our customer. Sofics’ IP offered a great solution and Sofics delivered it in just two weeks.”
Testimonial: Renesas – ZMDI
- Application-specific ICs for automotive and industrial electronics, …
- TSMC 0.18um BCD process
Frank Shulze, Business Line Manager, Sensing & Automotive
“Sofics’ clamps were superior in the EMC test, as well as in parameters such as meeting flexible clamping voltage specifications”
Further reading
- Blog articles about high voltage tolerance
- Blog article “3 approaches to handle EOS requirements“
- Blog article “Sofics clipping circuit“
- Press release about 3.3V capable I/O in 28nm