For a number of interfaces the conventional ESD protection (2 diodes) is not possible. Specifically the diode from I/O to Vdd causes a lot of issues. Fortunately other ESD concepts are available.
ICs manufactured on advanced nodes like FinFET processes only support I/Os up to 1.8V. However, for communication with legacy chips higher voltages are required like 3.3V or even 5V.
Sometimes system makers demand high EOS and surge tolerance voltages, beyond the GPIO capabilities.
Sofics has delivered unique ESD protection clamps for many projects when the customer designed the functional I/O circuit. More recently, Sofics has also designed several functional I/O circuits with higher voltage capabilities.
Contact us (info@sofics.com) to discuss your application.
We can protect open-drain, hot-swap, fail-safe and cold-spare interfaces.
Examples in different processes
Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.
All cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.
Mature CMOS (0.5um to 180nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 180nm | 5V I/O | > 8 kV HBM | < 5 nA |
| TSMC 180nm | 7V I/O | > 2 kV HBM | < 50 nA |
Mainstream CMOS (130nm to 65 nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 130nm | 5V I/O | > 3 kV HBM | < 5 nA |
| TSMC 130nm | 7V I/O | > 4 kV HBM | < 1 nA |
| TSMC 65nm | 5V I/O | > 4 kV HBM | < 1 nA |
| TSMC 65nm | 5V I/O | > 4 kV HBM | < 100 nA |
Advanced CMOS (40 to 22nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 40nm | 5V I/O | > 2 kV HBM | < 10 nA |
| TSMC 28nm | 3.9V I/O | > 2 kV HBM | < 50 pA |
| TSMC 28nm | 5.5V I/O | > 2 kV HBM | < 400 pA |
| TSMC 28nm | 6.5V I/O | > 2 kV HBM | < 400 pA |
| TSMC 28nm | 12V I/O | > 2 kV HBM | < 40 nA |
| UMC 28nm | 8.6V I/O | > 500 kV HBM | < 1 nA |
FinFET technology
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 16nm | 5V I/O | > 1 kV HBM | < 30 nA |
| TSMC 12nm | 5V I/O | > 4 kV HBM | < 3 uA |
BiCMOS technology
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| GF 22FDX | 3.3V I/O | > 2 kV HBM | < 500 pA |
These are examples from many IP delivery projects. If you did not find the example you were looking for you should
Contact us (info@sofics.com) to discuss your application and requirements.
We can protect open-drain, hot-swap, fail-safe and cold-spare interfaces.
Further reading
- Blog article “3 problems with diode based ESD“
- Blog article “Not all overvoltage tolerant GPIOs are the same“
- Blog article “6 concepts to replace dual diode ESD“
- Blog article “Local ESD protection for analog I/Os“