Fabless companies that integrate Sofics IP in their IC designs have been able to reduce their costs spanning across reduced design cost, reduced mask and manufacturing costs, lower risks and reduced time-to-market. Below are examples how this was achieved.
On-chip ESD/EOS/Latch up protection for advanced and low voltage processes
Design cost reduction
Mask cost reduction
Designing ESD protection can be very costly: typically many test structures are required, analysis needs to be done, IP positions need to be checked and respected…. Sofics has a wide range of solutions, for a wide range of applications, silicon proven in a wide range of processes. As an IP provider, we can distribute the ESD design cost over many different customers, lowering the cost for everyone.
It’s at the core of Sofics’ philosophy that process technologies are designed for IC performance, not for ESD protection. Therefore, we work only with the masks required for the performance of the IC. Layers such as silicide block or DeepNwell are used only if the product requires them for other performance reasons.
Solutions proven in 9 generations of CMOS technology – broad product ready portfolio.
Sofics designs do not need an ESD implant.
Manufacturing cost reduction
Speed up time-to-market
Sofics has an extensive experience in minimizing silicon area – in fact, area reduction was the first value statement made to customers when starting the business in the early 2000’s. Today still many customers profit from this expertise, beneficial for most applications, critical for some, such as smartcards or panel display drivers.
Designing ESD protection can be very time consuming: often at least one silicon run is required, often setting back the IC design for a couple of months. Sofics has a wide range of solutions, for a wide range of applications, silicon proven in a wide range of processes, readily available at your fingertips.
$10’s to $100’s per wafer cost reduction – in volume production.
Less than 1 month from first contact to contract delivery of first time right solutions – achieved.
Risk reduction
Proven portability
Tape outs are expensive, especially in the most advanced nodes. But for an application such as Machine Learning, the required high computing power forces the choice for (e.g.) 16nm FinFET technologies. Several customers work with Sofics merely to lower the risk of re-spins – an effective cost reduction.
Sofics has many customers using our solution in multiple process technologies. The porting can be done by the customer, or by Sofics, whatever our customers prefer. But having a solution and strategy that lasts for many process generations (down to 16nm FinFETs today) is a clear cost saver.
Not spinning silicon/designs for many months – priceless achievement and benefit.
Consistency of solution strategy across process generations.