Category: ESD design window
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Selecting optimized ESD protection for CMOS image sensors
Today, you can find CMOS image sensors almost everywhere in consumer, automotive, health and security applications. There has been a lot of innovation to enable demanding requirements. The article provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for…
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3 approaches to handle EOS ‘requirements’
EOS, or Electrical Overstress, is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product. It is important to discuss because many products are damaged this way. This article includes case studies and 3 approaches to handle those requests.
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Introduction: ESD protection concepts for I/Os
There are many different approaches to ensure effective ESD protection for integrated circuits. It is important to select the right approach for each interface and power domain. This article outlines the main options for Interface protection.
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Time to say farewell to the snapback ggNMOS for ESD protection
For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below). However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.
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Introduction about ESD protection: basic concepts to advanced applications
Koen Decock, ESD design specialist at Sofics, made a presentation for a full auditorium, organized by the local IEEE SSCS student chapter in Leuven. He talked about on-chip ESD protection, from the basic concepts to the more advanced applications.