Area reduction opportunities for ESD protection

There are many benefits when using Sofics ESD protection clamps like flexibility, lower leakage and lower capacitance. One benefit that is directly connected to cost reduction is the ability to reduce the silicon footprint of the ESD clamps compared to traditional approaches.

Sofics engineers have developed ESD clamps that are a lot smaller in CMOS, SOI, FinFET, Nanosheet and BCD process technologies.

Contact us (info@sofics.com) to discuss your application.
We can reduce the area of the ESD clamps.

Examples in different processes

In the past 25 years Sofics engineers have developed novel protection clamps. These innovative concepts are compatible with the foundry process but provide benefits like lower capacitance, lower leakage, more flexibility and scalable ESD robustness. For many customers the main benefit is the reduced area compared to traditional ESD clamps. Specifically for designs that demand high ESD robustness the area reduction potential is significant.

BCD technology

Sofics has verified its PowerQubic devices on several foundry and IDM processes.

Example 1: Area reduction compared to foundry based ESD protection on TSMC 180nm BCD technology. In the project the customer required an ESD protection for an automotive LIN transceiver interface with trigger voltage (Vt1) and holding voltage (Vh) above 40V.

ESD requirement	Area reduction by Sofics IP
2 kV HBM	25% smaller
4 kV HBM	40% smaller
8 kV HBM	50% smaller
8 kV IEC 61000-4-2	55% smaller

Example 2: Area reduction compared to foundry based ESD protection on TSMC 180nm BCD technology for different voltage domains.

ESD requirement	12V case	20V case	36V case	45V case
2 kV HBM	75% smaller	65% smaller	65% smaller	60% smaller
4 kV HBM	80% smaller	75% smaller	75% smaller	70% smaller
8 kV HBM	85% smaller	80% smaller	80% smaller	75% smaller
8 kV IEC 61000-4-2	>85% smaller	>85% smaller	85% smaller	80% smaller

FinFET technology

On our 3nm test chip we compared the traditional RC BIGFet ESD protection with our own novel concept. We reached an amazing 66% reduction in area for the 0.75V rail clamp. The IP can be transferred to other CMOS and FinFET processes. More background is available in our blog article.

ESD robustness	Area
8 kV HBM	1151 um²
6 kV HBM	912 um²
4 kV HBM	680 um²
2 kV HBM	433 um²

These are examples from many IP delivery projects. If you did not find the example you were looking for you should
Contact us (info@sofics.com) to discuss your application and requirements.
We can reduce the area of the ESD clamps.

Testimonial: Altera – Intel company

FPGA product families
180nm, 130nm, 90nm, 65nm, 40nm and 28nm processes
ESD for multi-voltage and high-speed SerDes

Bradley Howe, vice president of IC Design

“We chose Sofics technology for our FPGA product families to deliver high-performance, cost-effective programmable products.

Sofics has allowed us to effectively manage
both ESD protection and IO area.”

Testimonial: Seiko Epson

High voltage Driver ICs
LCD panels of different sizes, pixel counts

Yoshiyuki Miyayama, General Manager IC Technology Department

“By utilizing Sofics IP in our HV-CMOS devices, we will be able to offer new ICs even faster than before and achieve a substantial reduction of the on-chip I/O area”

Testimonial: Toshiba Semiconductor

Hundreds of ASIC designs
180nm to 40nm CMOS technology
All kinds of applications

Shigeo Koguchi, Toshiba Semiconductor Company

“Sofics technology helps us reduce the die size of our chips, while maintaining and ensuring ESD protection in all application areas including high speed. We’ve had consistent success in designing more compact, higher-performance ESD protection into our ICs.”