Sofics technology has been applied for many different applications. Some applications need I/O circuits and ESD protection that can tolerate a higher voltage.
ICs manufactured on advanced nodes like FinFET processes only support I/Os up to 1.8V. However, for communication with legacy chips higher voltages are requirded like 3.3V or even 5V.
Another reason for higher voltage tolerance comes from the requirement to power the chips from USB or batteries at 4.5V – 5V.
Sometimes system makers demand high EOS and surge tolerance voltages, beyond the GPIO capabilities.
Sofics has delivered unique ESD protection clamps for many different projects when the customer designed the functional I/O circuit. More recently, Sofics has also designed several functional I/O circuits with higher voltage capabilities.
Examples in different processes
Examples for ESD protection clamps on different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.
Cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.
Mature CMOS (0.5um to 180nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 180nm | 5V rail | > 8 kV HBM | < 5 nA |
| TSMC 180nm | 5V I/O | > 8 kV HBM | < 5 nA |
| TSMC 180nm | 7V I/O | > 2 kV HBM | < 50 nA |
| TowerSemi 350nm | 4.5V rail | > 8 kV HBM | < 100 nA |
Mainstream CMOS (130nm to 65 nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 130nm | 5V rail | > 3 kV HBM | < 1 nA |
| TSMC 130nm | 5V I/O | > 3 kV HBM | < 1 nA |
| TSMC 130nm | 7V I/O | > 4 kV HBM | < 1 nA |
| TSMC 65nm | 5V I/O OVT | > 4 kV HBM | < 1 nA |
| TSMC 65nm | 5V I/O | > 4 kV HBM | < 100 nA |
Advanced CMOS (40 to 22nm)
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 40nm | 5V rail | > 2 kV HBM | < 10 nA |
| TSMC 40nm | 5V I/O | > 2 kV HBM | < 10 nA |
| TSMC 28nm | 3.9V I/O | > 2 kV HBM | < 50 nA |
| TSMC 28nm | 5.5V I/O | > 2 kV HBM | < 400 nA |
| TSMC 28nm | 6.5V I/O | > 2 kV HBM | < 400 nA |
| TSMC 28nm | 12V I/O | > 2 kV HBM | < 40 nA |
| UMC 28nm | 8.6V I/O | > 200 V HBM | < 1 uA |
FinFET technology
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| TSMC 16nm | 5V rail | > 1 kV HBM | < 30 nA |
| TSMC 16nm | 5V I/O | > 1 kV HBM | < 30 nA |
| TSMC 12nm | 3.3V rail | > 3 kV HBM | < 60 nA |
| TSMC 12nm | 5V I/O | > 4 kV HBM | < 3 uA |
| TSMC 7nm | 3.3V rail | > 2 kV HBM | < 1.5 uA |
| TSMC 5nm | 1.8V rail | > 1 kV HBM | < 500 pA |
SOI technology
| Process | Pad | ESD robustness | Leakage |
|---|---|---|---|
| GF 22FDX | 3.3V rail | > 5 kV HBM | < 10 pA |
| GF 22FDX | 3.3V I/O | > 2 kV HBM | < 500 pA |
| GF 22FDX | 5V rail | > 4 kV HBM | < 10 nA |
Further reading
Blog articles about high voltage tolerance
Blog article “3 approaches to handle EOS requirements“
Blog article “Sofics clipping circuit“
Press release about 3.3V capable I/O in 28nm