Low leakage

Sofics technology has been applied for many different applications. Some applications require ESD solutions with (much) lower leakage compared to the conventional ESD clamps.

For instance, in IoT (Internet of Things) or medical circuits designers want to reduce total power consumption. Also for wireless interfaces, lower leakage improves the Q-factor for LNA circuits. Some high-impedance sensor interfaces need (ultra-low) leakage to ensure the bias levels are not affected.

Sofics ESD cells have orders of magnitude lower leakage (nano-Amps instead of micro-amps). Examples from different projects are shown and listed below.

Contact us (info@sofics.com) to discuss your application. We can help reduce the power consumption of your interface circuits

Log-log plot showing leakage number versus ESD robustness from different IP delivery projects, across foundries, process nodes. In many cases the Sofics IP achieves a drastic reduction of leakage current compared to traditional ESD solutions in the PDK.

Examples in different processes

Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.

All cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process and voltage level.

Mature CMOS (0.5um to 180nm)

Process	Pad	ESD robustness	Leakage
TSMC 180nm	1.8V rail	> 5 kV HBM	< 200 pA
TSMC 180nm	1.8V I/O	> 5 kV HBM	< 200 pA
TSMC 180nm	5V rail	> 8 kV HBM	< 5 nA
TSMC 180nm	5V I/O	> 8 kV HBM	< 5 nA
TSMC 180nm	7V I/O	> 2 kV HBM	< 50 nA
TowerSemi 350nm	4.5V I/O	> 8 kV HBM	< 100 nA

Mainstream CMOS (130nm to 65 nm)

Process	Pad	ESD robustness	Leakage
TSMC 130nm	1.0V I/O	> 4 kV HBM	< 50 pA
TSMC 130nm	1.0V rail	> 3 kV HBM	< 50 pA
TSMC 130nm	3.3V I/O	> 3 kV HBM	< 10 pA
UMC 130nm	1.2V I/O	> 2 kV HBM	< 10 nA
TSMC 90nm	1.8V rail	> 2 kV HBM	< 0.5 nA
TSMC 65nm	1.0V I/O	> 4 kV HBM	< 1 nA
TSMC 65nm	1.2V rail	> 2 kV HBM	< 100 pA
GF 65nm	1.0V I/O	> 2 kV HBM	< 50 nA
GF 65nm	1.8V I/O	> 3 kV HBM	< 100 pA

Advanced CMOS (40 to 22nm)

Process	Pad	ESD robustness	Leakage
TSMC 40nm	0.9V rail	> 2 kV HBM	< 100 pA
TSMC 28nm	0.85V I/O	> 2 kV HBM	< 50 pA
TSMC 28nm	3.3V I/O	> 200 V HBM	< 40 pA

Example: comparing the foundry ESD solution to the Sofics approach on a 40nm CMOS process

Foundry library

Foundry provided, standard GPIO library

leakage: 100 nA
Typical improvement: high Vt devices

Sofics approach

Comparable Sofics ESD clamp

Leakage: 25 pA
400x lower leakage

SOI technology

Process	Pad	ESD robustness	Leakage
GF 22FDX	1.2V rail	> 2 kV HBM	< 30 pA
GF 22FDX	1.2V I/O	> 2 kV HBM	< 50 pA
GF 22FDX	1.8V rail	> 2 kV HBM	< 50 pA
GF 22FDX	1.8V I/O	> 2 kV HBM	< 150 pA
GF 22FDX	3.3V rail	> 5 kV HBM	< 10 pA
GF 22FDX	3.3V I/O	> 2 kV HBM	< 500 pA

FinFET technology

Process	Pad	ESD robustness	Leakage
TSMC 16nm	0.8V SerDes interface	> 2 kV HBM	< 10 nA at 125°C
TSMC 16nm	0.9V power clamp	> 2 kV HBM	< 80 pA
TSMC 16nm	1.8V power clamp	> 2 kV HBM	< 300 pA
TSMC 16nm	1.8V power clamp	> 4 kV HBM	< 500 pA
TSMC 12nm	0.8V power clamp	> 3 kV HBM	< 10 nA at 125°C
TSMC 12nm	1.8V Interface	> 3 kV HBM	< 10 nA at 125°C
TSMC 12nm	2.5V interface	> 3kV HBM	< 10 nA
TSMC 12nm	3.3V interface	> 3kV HBM	< 50 nA
TSMC 7nm	0.75V power clamp	> 2 kV HBM	< 300 pA
TSMC 7nm	0.85V I/O	> 2 kV HBM	< 50 pA
TSMC 7nm	0.9V SerDes interface	> 150 V HBM	< 10 pA
TSMC 5nm	0.75V power clamp	> 2 kV HBM	< 15 nA
TSMC 5nm	0.75V interface	> 1.5 kV HBM	< 50 pA
TSMC 5nm	1V SerDes interface	> 1.5 kV HBM	< 1 nA
TSMC 5nm	1.2V power clamp	> 2 kV HBM	< 50 nA
TSMC 5nm	1.5V power clamp	> 1 kV HBM	< 10 nA
TSMC 5nm	1.5V interface	> 1 kV HBM	< 500 pA
TSMC 5nm	1.8V power clamp	> 1 kV HBM	< 500 pA
Samsung 4nm	0.75V power clamp	> 5 kV HBM	< 500 pA
Samsung 4nm	1.2V power clamp	> 10 kV HBM	< 250 pA
Samsung 4nm	1.2V interface	> 5 kV HBM	< 150 pA
Samsung 4nm	1.8V power clamp	> 12 kV HBM	< 30 nA
Samsung 4nm	1.8V interface	> 5 kV HBM	< 150 pA
Samsung 4nm	3.3V power clamp	> 7 kV HBM	< 5 nA
Samsung 4nm	3.3V interface	> 5 kV HBM	< 150 pA

Nanosheet technology

Process	Pad	ESD robustness	Leakage
TSMC 2nm	1.2V rail	> 5 kV HBM	< 42 nA
TSMC 2nm	1.2V rail	> 6 kV HBM	< 7.5 nA
TSMC 2nm	1.5V rail	> 6 kV HBM	< 20 nA
TSMC 2nm	1.8V rail	> 6 kV HBM	< 17 nA
TSMC 2nm	1.2V I/O	> 3 kV HBM	< 9 nA
TSMC 2nm	1.8V I/O	> 6 kV HBM	< 150 nA

These are examples from many different IP delivery projects. If you did not find the example you were looking for you should contact us (info@sofics.com) to discuss your application and requirements.
We can help reduce the power consumption of your interface circuits

Testimonial: ONiO

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