
Sofics technology has been applied for many different applications. A number of applications require ESD solutions with (much) lower leakage compared to the conventional ESD clamps.
For instance, in IoT or medical circuits designers want to reduce total power consumption. In wireless applications, lower leakage improves the Q-factor for LNA circuits. Some high-impedance sensor interfaces need (ultra-low) leakage to ensure the bias levels are not affected.
Sofics ESD cells have orders of magnitude lower leakage (nano-Amps instead of micro-amps).
Examples in different processes
Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.
All cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.
Mature CMOS (0.5um to 180nm)
Process | Pad | ESD robustness | Leakage |
---|---|---|---|
TSMC 180nm | 1.8V rail | > 5 kV HBM | < 200 pA |
TSMC 180nm | 1.8V I/O | > 5 kV HBM | < 200 pA |
TSMC 180nm | 5V rail | > 8 kV HBM | < 5 nA |
TSMC 180nm | 5V I/O | > 8 kV HBM | < 5 nA |
TSMC 180nm | 7V I/O | > 2 kV HBM | < 50 nA |
TowerSemi 350nm | 4.5V I/O | > 8 kV HBM | < 100 nA |
Mainstream CMOS (130nm to 65 nm)
Process | Pad | ESD robustness | Leakage |
---|---|---|---|
TSMC 130nm | 1.0V I/O | > 4 kV HBM | < 50 pA |
TSMC 130nm | 1.0V rail | > 3 kV HBM | < 50 pA |
TSMC 130nm | 3.3V I/O | > 3 kV HBM | < 10 pA |
UMC 130nm | 1.2V I/O | > 2 kV HBM | < 10 nA |
TSMC 90nm | 1.8V rail | > 2 kV HBM | < 0.5 nA |
TSMC 65nm | 1.0V I/O | > 4 kV HBM | < 1 nA |
TSMC 65nm | 1.2V rail | > 2 kV HBM | < 100 pA |
GF 65nm | 1.0V I/O | > 2 kV HBM | < 50 nA |
GF 65nm | 1.8V I/O | > 3 kV HBM | < 100 pA |
Advanced CMOS (40 to 22nm)
Process | Pad | ESD robustness | Leakage |
---|---|---|---|
TSMC 40nm | 0.9V rail | > 2 kV HBM | < 100 pA |
TSMC 28nm | 0.85V I/O | > 2 kV HBM | < 50 pA |
TSMC 28nm | 3.3V I/O | > 200 V HBM | < 40 pA |
Comparing the foundry ESD solution to the Sofics approach on a 40nm CMOS process
Foundry library
Foundry provided, standard GPIO library
- leakage: 100 nA
- Typical improvement: high Vt devices

Sofics approach
Comparable Sofics ESD clamp
- Leakage: 25 pA
- 400x lower leakage

SOI technology
Process | Pad | ESD robustness | Leakage |
---|---|---|---|
GF 22FDX | 1.2V rail | > 2 kV HBM | < 30 pA |
GF 22FDX | 1.2V I/O | > 2 kV HBM | < 50 pA |
GF 22FDX | 1.8V rail | > 2 kV HBM | < 50 pA |
GF 22FDX | 1.8V I/O | > 2 kV HBM | < 150 pA |
GF 22FDX | 3.3V rail | > 5 kV HBM | < 10 pA |
GF 22FDX | 3.3V I/O | > 2 kV HBM | < 500 pA |
FinFET & FDSOI technology
Further reading
Blog articles where “low leakage ESD clamps” aspects are discussed.
Blog article “ESD protection for Internet-of-Things“
Blog article “Medical applications“