Open-drain hot-swap fail-safe

For a number of interfaces the conventional ESD protection (2 diodes) is not possible. Specifically the diode from I/O to Vdd causes a lot of issues. Fortunately other ESD concepts are available.

Examples in different processes

Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.
All cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.

Mature CMOS (0.5um to 180nm)

Process	Pad	ESD robustness	Leakage
TSMC 180nm	5V I/O	> 8 kV HBM	< 5 nA
TSMC 180nm	7V I/O	> 2 kV HBM	< 50 nA

Mainstream CMOS (130nm to 65 nm)

Process	Pad	ESD robustness	Leakage
TSMC 130nm	5V I/O	> 3 kV HBM	< 5 nA
TSMC 130nm	7V I/O	> 4 kV HBM	< 1 nA
TSMC 65nm	5V I/O	> 4 kV HBM	< 1 nA
TSMC 65nm	5V I/O	> 4 kV HBM	< 100 nA

Advanced CMOS (40 to 22nm)

Process	Pad	ESD robustness	Leakage
TSMC 40nm	5V I/O	> 2 kV HBM	< 10 nA
TSMC 28nm	3.9V I/O	> 2 kV HBM	< 50 pA
TSMC 28nm	5.5V I/O	> 2 kV HBM	< 400 pA
TSMC 28nm	6.5V I/O	> 2 kV HBM	< 400 pA
TSMC 28nm	12V I/O	> 2 kV HBM	< 40 nA
UMC 28nm	8.6V I/O	> 500 kV HBM	< 1 nA

FinFET technology

Process	Pad	ESD robustness	Leakage
TSMC 16nm	5V I/O	> 1 kV HBM	< 30 nA
TSMC 12nm	5V I/O	> 4 kV HBM	< 3 uA

BiCMOS technology

Process	Pad	ESD robustness	Leakage
GF 22FDX	3.3V I/O	> 2 kV HBM	< 500 pA