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Open-drain hot-swap fail-safe

For a number of interfaces the conventional ESD protection (2 diodes) is not possible. Specifically the diode from I/O to Vdd causes a lot of issues. Fortunately other ESD concepts are available.

Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.
All cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.

ProcessPadESD robustnessLeakage
TSMC 180nm5V I/O> 8 kV HBM< 5 nA
TSMC 180nm7V I/O> 2 kV HBM< 50 nA
ProcessPadESD robustnessLeakage
TSMC 130nm 5V I/O> 3 kV HBM< 5 nA
TSMC 130nm7V I/O> 4 kV HBM< 1 nA
TSMC 65nm5V I/O> 4 kV HBM< 1 nA
TSMC 65nm5V I/O> 4 kV HBM< 100 nA
ProcessPadESD robustnessLeakage
TSMC 40nm5V I/O> 2 kV HBM< 10 nA
TSMC 28nm3.9V I/O> 2 kV HBM< 50 pA
TSMC 28nm5.5V I/O> 2 kV HBM< 400 pA
TSMC 28nm6.5V I/O> 2 kV HBM< 400 pA
TSMC 28nm12V I/O> 2 kV HBM< 40 nA
UMC 28nm8.6V I/O> 500 kV HBM< 1 nA
ProcessPadESD robustnessLeakage
TSMC 16nm 5V I/O> 1 kV HBM< 30 nA
TSMC 12nm5V I/O> 4 kV HBM< 3 uA
ProcessPadESD robustnessLeakage
GF 22FDX3.3V I/O> 2 kV HBM< 500 pA

Blog article “3 problems with diode based ESD
Blog article “6 concepts to replace dual diode ESD
Blog article “Local ESD protection for analog I/Os