Tag: 65nm
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Sofics Datasheet – TSMC 65nm 3V3 GPIO – 2.5V / 3.3V Device Options
This specific IP macro is designed in TSMC 65nm LP and is available using either 3.3V or 2.5V I/O transistors. The 2.5V transistor option supports 3.3V VDDIO operation. Core supply VDD is 1.2V, with supported I/O modes from 1.8V to 3.3V. It can be ported to other technologies upon request…
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Sofics Datasheet – TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS65N-3V3-LC-LWC-RH-ESD] Key Highlights Details Parameter Value VDD 3.3V ±10% VDDIO VDD+0.3V ±10% Temperature Tj -55C to 125C Key Features Parameter Value TLP 1.33A…