People developing Data Center chips benefit from custom ESD protection solutions. The main bottleneck is the speed at which data can be transferred. To enable high-speed communication designers use thin-oxide transistors and low voltage signal protocols at the SerDes/PCIe interface.
In the past the short distance (between racks) connections relied on electrical communication while the long distance, between data centers, uses optical communication. These days even for the short distance optical communication is used.
There are several reasons why IC designers developing AI products require custom ESD solutions
High-speed communication between compute and memory require I/Os and ESD protection with low parasitic capacitance
Data center AI chips used for training new models are manufactured on the most advanced FinFET processes for the highest performance. The core transistors on these processes are very sensitive to ESD stress. Effective ESD protection clamps are required
AI chips are among the biggest ICs ever made. That is important to consider because the transient current during CDM stress is higher for bigger dies and packages.
To conserve energy, Edge AI applications should use low leakage ESD protection concepts
Sofics IP for Data Centers
Key Focus Areas
Die-2-die interface protection
Sofics IP is used for many high-speed data interfaces (wired and optical) between the compute and memory functions. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.
Fabless companies that integrate Sofics IP in their IC designs have been able to reduce their costs spanning across reduced design cost, reduced mask and manufacturing costs, lower risks and reduced time-to-market.
Low voltage signaling
High CSM stress levels
High frequency interfaces are built with thin oxide transistors. They also frequently run at a low signal voltage, below the standard I/O voltage range. Sofics has delivered ESD protection solutions for the most sensitive transistors on CMOS and FinFET processes and operating at a voltage of 1V or lower.
Data center chips are typically very large dies. However, the larger the package, the higher the peak current is during CDM stress events. Moreover, these chips rely on advanced FinFET processes that are most sensitive during those fast transient events. It is imperative to use fast, local ESD clamps to limit the voltage drop during fast transients.
Process technology covered
Advanced CMOS (40nm to 22nm)
IC products from our costumers
Our customers have created unique products. Several companies are developing modules for rack-to-rack communication based on optical interfaces.
Other customers focus on the compute aspects with high performance Artificial Intelligence functions. These huge chips rely on Sofics solutions for CDM protection.
Blog article “Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration“
Blog article “Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology“
Blog article “Optical communication also requires ESD protection“
ESD protection for FinFET processes
Press announcement about Sofics IP availability on TSMC 16nm, 12nm and 7nm FinFET nodes
Press announcement about Sofics IP available on TSMC 5nm FinFET
Press release about our cooperation with Graphcore (UK)