Tag: 0V75
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Sofics Datasheet – TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Multiple clamp variants enable trade-offs between ESD robustness, parasitic capacitance, leakage and silicon area, including options down to 10fF capacitance and 133.84µm² area. Sofics Datasheet –…
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Sofics Datasheet – SMIC 28nm 0V75 ESD Local Clamp – Low Capacitance
This specific IP macro is designed in 28nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-SMIC-28-0V75-LC-ESD] Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 0.75V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 1.33A HBM…
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Sofics Datasheet – TSMC 4nm 0V75 D2D AFE
This specific IP macro is designed in TSMC 4nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS4N-0V75-D2D-AFE Key Highlights Details Parameter Value VDD 0.75 V ±10% Temperature Tj -40 C to 105 C Key Features Parameter Value Rise time (10-90)1 <50 ps…