Tag: Power Clamp
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Sofics Datasheet – SMIC 28nm 0V75 ESD Power Clamp
This specific IP macro is designed in 28nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-SMIC-28-HKCp-0V75-PC-ESD] Key Highlights Details Parameter Value VDD 0.75V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 1.33A HBM 2kV CDM 6A…
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Sofics Datasheet – TSMC 12nm 2V5 ESD Power Clamp
This TSMC 12nm 2.5V ESD Power Clamp IP macro provides compact, low-leakage ESD protection for FinFET designs. It is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-2V5-PC-ESD] Key Highlights Details Parameter Value VDD 2.5V ±10%…
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Sofics Datasheet – TSMC 12nm 1V8 ESD Power Clamp
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-1V8-PC-ESD] Key Highlights Details Parameter Value VDD 1.8V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 1.33A HBM ±2.1kV Leakage…
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Sofics Datasheet – TSMC 12nm 5V0 ESD Power Clamp
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-5V0-PC-ESD] Key Highlights Details Parameter Value VDD 5.0V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 3.0A HBM ±4.5kV CDM…
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Sofics Datasheet – TSMC 2nm 1V8 ESD Power Clamp – Low Leakage
This specific IP macro is designed in TSMC 2nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS2-1V8-PC-LL-ESD] Key Highlights Details Parameter Value VDD 1.8V ±10% Temperature Tj -40C to 125C Key Features Parameter Value Leakage <14nA TLP 4.82A HBM…