Designers working on chips for Articificial Intelligence (AI) benefit from custom ESD protection solutions. For many AI applications one of the main bottleneck is the speed at which data to be processed can be moved to the compute functions. To enable high-speed communication designers use thin-oxide transistors and low voltage signal protocols at the SerDes/PCIe interface.
There are several reasons why IC designers developing AI products require custom ESD solutions
High-speed communication between compute and memory require I/Os and ESD protection with low parasitic capacitance
Data center AI chips used for training new models are manufactured on the most advanced FinFET processes for the highest performance. The core transistors on these processes are very sensitive to ESD stress. Effective ESD protection clamps are required
AI chips are among the biggest ICs ever made. That is important to consider because the transient current during CDM stress is higher for bigger dies and packages.
To conserve energy, Edge AI applications should use low leakage ESD protection concepts
Sofics IP for AI
Key Focus Areas
Die-2-die interface protection
Sofics IP is used for many high-speed data interfaces (wired and optical) between the compute and memory functions. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.
To shorten the distance and delay between memory and compute functions some customers are using 3D stacking of different dies in a single assembly. The connections between the different dies (die-2-die interfaces) require custom ESD solutions.
Battery powered applications
High CDM stress levels
Besides AI chips used for training in datacenters there is also a market for AI inference chips used at the edge, close to sensors. For those chips the power consumption must be reduced. The leakage of Sofics’ ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.
Datacenter AI chips are typically very large dies. However, the larger the package, the higher the peak current is during CDM stress events. Moreover, these chips rely on advanced FinFET processes that are most sensitive during those fast transient events. It is imperative to use fast, local ESD clamps to limit the voltage drop during fast transients.
Process technology covered
Advanced CMOS (40nm to 22nm)
IC products from our costumers
Our customers have created unique products in the AI domain. Examples include ultra-low power edge AI products that can for instance be used in audio applications and AI chips for the most performant data centers. Several companies are developing AI products that rely on optical interfaces. That can help to create faster links between memory and compute functions but others develop optical compute functionality.
Blog article “Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration“
Blog article “Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology“
Blog article “Optical communication also requires ESD protection“
Blog article “ESD protection for FinFET processes“
Press release about our cooperation with Graphcore (UK)