Chiplets and Die-to-Die Interfaces: Scalable ESD and I/O Protection

The semiconductor industry is moving rapidly toward chiplet-based designs. By integrating multiple dies in a single package, companies can enhance performance, reduce power consumption, shrink system footprint, and accelerate development cycles.

These 2.5D and 3D hybrid integrations introduce new challenges — especially in ESD protection. While die-to-die interfaces may not face external ESD stress post-assembly, the ESD requirements shift, requiring custom, scalable solutions.

Sofics provides tailored ESD and I/O IP specifically designed for die-to-die links in chiplet-based systems. Our IP is already proven in AI chips, silicon photonics, and advanced computing platforms.

Custom Requirements for Chiplets

5 key reasons chiplet (die-2-die) interfaces require specialty I/O circuits and custom ESD protection:

Voltage/current range
Die-2-die interfaces operate outside the typical GPIO voltage range. They run at a lower voltage (1V or lower) and can use a much reduced drive current
Thin oxide transistors
For speed, D2D interfaces are designed with thin-oxide transistors. Those are easily damaged during ESD events
High speed interfaces
The parasitic capacitance of ESD protection in traditional GPIOs is too high for high bandwidth D2D interfaces
Silicon area
Standard I/O pads consume too much silicon area when Chiplet interfaces require thousands of D2D connections
Lower ESD robustness
ESD clamps integrated in traditional GPIOs are designed for >2kV HBM while D2D interfaces only need a fraction of that

Sofics IP for chiplets, die-2-die interfaces

Key focus areas

High-speed interfaces
Low-capacitance ESD protection for optical and electrical interconnects
FinFET-compatible local clamps
Optimized for the most sensitive nodes
Low-voltage interface support
IP designed for signal levels of 1V or even lower, using thin-oxide transistors
Customizable ESD robustness
Easily tuned for intra-package requirements, reducing area and design overhead

Process technology cover

Mature CMOS (0.5um to 180nm)
Mainstream CMOS (130nm to 65nm)
Advanced CMOS (40nm to 22nm)
FinFET technology
SOI technology
BiCMOS technology

Foundries covered

TSMC
UMC

IC products from our customers

Sofics IP protects die-to-die links across a variety of high-performance ICs:

AI accelerators
Our ESD IP protects optical communication links between compute and memory die in chiplet-based AI processors.
Silicon photonics modules
Combining optical and electrical dies in a single package, with 15+ successful customer projects supported.
3D stacked camera chips
CMOS image sensor, logic and memory combined
Accurate timing chips
Combination of logic and MEMS oscillator

These are examples from many IP delivery projects. If you did not find the example you were looking for you should contact us (info@sofics.com) to discuss your application and requirements.