Chip designers working on ICs produced at UMC can use the (free) General Purpose I/O (GPIO) library for the chip interfaces. These GPIOs also include conventional ESD protection devices.

However, for some applications this traditional ESD approach limits the designer. Constraints include high leakage, high parasitic capacitance, large area, fixed ESD robustness and limited signal voltage options.

Sofics IP for UMC

Sofics IP is used for many high-speed data interfaces (wireless, wired and optical). These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

To shorten the distance and delay between different functions some customers are using 3D stacking of different dies in a single assembly. The connections between the different dies (die-2-die interfaces) require custom ESD solutions.

For certain applications like IoT, edge AI, medical devices, the power consumption must be reduced. The leakage of Sofics’ ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.

Some applications require higher ESD robustness, well beyond the typical 2kV HBM. Our ESD clamps can be easily scaled to any ESD/EOS protection level. We have delivered ESD clamps for 4kV, 8kV HBM as well as for 8kV IEC 61000-4-2.

Applications designed on advanced CMOS or FinFET processes typically use low signal voltages below 2V. However, there are several reasons that designers want to use a higher signal voltage like 3.3V, 5V or even higher. Sofics has developed ESD devices and I/O circuits that can handle those requirements.

Integrated circuits used in space, nuclear physics research or several medical applications require a higher tolerance against radiation. The conventional I/O circuits and ESD devices degrade under this kind of stress. Fortunately, Sofics has proven solutions.