Why IC designers need custom ESD cells
Chip designers working on ICs produced at HHGrace can use the (free) General Purpose I/O (GPIO) library for the chip interfaces. These GPIOs also include conventional ESD protection devices.
However, for some applications this traditional ESD approach limits the designer. Constraints include high leakage, high parasitic capacitance, large area, fixed ESD robustness and limited signal voltage options.
Sofics IP for HHGrace
Process technology covered
Key focus areas
High signal voltage tolerance
Battery powered applications
Applications designed on CMOS processes typically use low signal voltages below 3.3V. However, there are several reasons that designers want to use a higher signal voltage like 5V or even higher. Sofics has developed ESD devices that can handle those requirements.
For certain applications like IoT, edge AI, medical devices, the power consumption must be reduced. The leakage of Sofics’ ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.
Enhanced ESD robustness
Some applications require higher ESD robustness, well beyond the typical 2kV HBM. Our ESD clamps can be easily scaled to any ESD/EOS protection level. We have delivered ESD clamps for 4kV, 8kV HBM as well as for 8kV IEC 61000-4-2.