Tag: 3nm
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Sofics Datasheet – TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-1V2-LC-ESD] Key Highlights Details…
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Sofics Datasheet – TSMC 3nm 3V3 ESD Local Clamp
This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-3V3-LC-ESD] Key Highlights Details Parameter…
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Sofics Datasheet – TSMC 3nm 3V3 GPIO
This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS3N-3V3GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 3.3V ±10% Temperature…
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Sofics Datasheet – TSMC 3nm 1V8 GPIO
This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS4N-1V8GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 1.8V ±10% Temperature…