Sofics Datasheet – TSMC 3nm 3V3 GPIO

This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

DS-TS3N-3V3GPIO

Key Highlights

Broad portfolio of IO configurations from a single base architecture
Modular design enables fast and reliable turnaround and low NRE
Proven across multiple advanced nodes
Optimized for performance, power, and area trade-offs

Details

Parameter	Value
VDD	0.75V ±10%
VDDIO	3.3V ±10%
Temperature Tj	-40°C to 125°C

Key Features

Parameter	Value
Maximum bit rate	>110Mbaud/s @ 5pF
Power consumption	< 5µW
Drive strength	5mA (other options available)
ESD robustness	2kV HBM \| 500V CDM

Area

Type	Size [µm²]
I/O	8000 – 10000

Summary

The TSMC 3nm 3.3V GPIO offers configurable I/O functionality with multi-voltage support, over-voltage tolerance (OVT), and high-speed or ultra-low-power modes. Designed for advanced nodes, it enables reliable interfacing between low-voltage cores and higher-voltage or legacy systems.

An integrated voltage regulator ensures stable operation across wide voltage ranges for auxiliary supply domains, supporting multi-voltage and OVT functionality without external components.

Pin Schematic

Features

Overvoltage tolerant design
Supports multiple supply voltages
Input enable/disable
Tri-state output
Pull select | Pullup/Pulldown
Compatible with TSMC I/O ring
Integrated voltage regulator
Other analog features such as slew rate control, fail-safe, drive strength options and more

Sofics offers a broad portfolio of configurable specialty I/Os enabling flexible integration across multiple voltage domains and applications. Explore our specialty GPIO circuits and TSMC IP solutions. Additional variants and features can be supported upon request, allowing fast customization through minimal design changes. For more information, visit www.sofics.com or contact us at bd@sofics.com.