Tag: TSMC
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Sofics Datasheet – TSMC 22nm 1.0V, 1.2V & 1.8V GPIO
This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS22N-1V0-1V2-1V8-GPIO Key Highlights Details Parameter Value VDD 1.8V – 3V3 ±10% VDDIO 1.0 ±10%1.2 ±10%1.8 ±10% Temperature Tj -40°C to 125°C Key Features Parameter Value Maximum…
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Sofics Datasheet – TSMC 7nm 2V5 ESD Local Clamp
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. The 2.5V local clamp provides 1.33A TLP, 2kV HBM and 5A CDM performance with 10nA leakage at 25C. Its compact 1600µm² implementation supports local protection for…
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Sofics Datasheet – TSMC 7nm 3V3 ESD Local Clamp
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. The 3.3V local clamp provides 2.35A TLP, 3.5kV HBM and 5A CDM performance with leakage below 50nA at 25C. Its compact 1800µm² implementation supports local protection…
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Sofics Datasheet – TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Multiple clamp variants enable trade-offs between ESD robustness, parasitic capacitance, leakage and silicon area, including options down to 10fF capacitance and 133.84µm² area. Sofics Datasheet –…
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Sofics Datasheet – TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS65N-3V3-LC-LWC-RH-ESD] Key Highlights Details Parameter Value VDD 3.3V ±10% VDDIO VDD+0.3V ±10% Temperature Tj -55C to 125C Key Features Parameter Value TLP 1.33A…
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Sofics Datasheet – TSMC 22nm 5V5 ESD Power Clamp – Low Leakage
This TSMC 22nm 5.5V ESD Power Clamp provides low-leakage protection for sensitive supply and interface pins. The IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS22N-5V5-LL-ESD] Key Highlights Details Parameter Value VDD 5.5V…
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Sofics Datasheet – TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
This TSMC 3nm 1.8V, 1.2V and 0.9V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins. It is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-1V8-1V2-0v9-LC-LWC01-ESD] Key Highlights Details Parameter…
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Sofics Datasheet – TSMC 22nm 5V0 GPIO
This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS22N-5V0-GPIO Key Highlights Details Parameter Value VDD 0.8V ± 10% VDDIO 5V ± 10% Temperature Tj -40°C to 105°C Key Features Parameter Value Maximum bit rate…
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Sofics Datasheet – TSMC 4nm 0V75 D2D AFE
This specific IP macro is designed in TSMC 4nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS4N-0V75-D2D-AFE Key Highlights Details Parameter Value VDD 0.75 V ±10% Temperature Tj -40 C to 105 C Key Features Parameter Value Rise time (10-90)1 <50 ps…
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Sofics Datasheet – TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-1V2-LC-ESD] Key Highlights Details…