Sofics Datasheet - TSMC 40nm 5V GPIO

This specific IP macro is designed in 40nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

Sofics Datasheet – [DS-TS40N-5V-GPIO]

Key Highlights

Broad portfolio of IO configurations from a single base architecture
Modular design enables fast and reliable turnaround and low NRE
Proven across multiple advanced nodes
Optimized for performance, power, and area trade-offs

Details

Parameter	Value
VDD	1.1V ±10%
VDDIO	5V ±10%
Temperature Tj	-40C to 105C

Key Features

Parameter	Value
Maximum bit rate	50MHz @ 5pF
Power consumption	2nA
Drive strength	4mA (other options available)
ESD robustness	6kV HBM \| 500V CDM

Area

Type	Size [μm²]
IO	13384

Summary

Sofics specialty I/Os offer configurable GPIOs with multi-voltage support, over-voltage tolerance (OVT), and high-speed or ultra-low-power modes. Designed for advanced nodes, they enable reliable interfacing between low-voltage cores and higher-voltage or legacy systems.

An integrated voltage regulator ensures stable operation across wide voltage ranges, for auxiliary supply domains, supporting multi-voltage and OVT functionality without external components.

Pin Schematic

Features

Overvoltage tolerant design
Supports multiple supply voltages
Input enable/disable
Tri-state output
Pull select | Pull-up/Pull-down
Compatible with foundry I/O ring
Integrated voltage regulator
Other analog features such as I2C, I3C, SPI, UART, JTAG, PWM, WDT, slew rate control, fail-safe, drive strength options and more

Sofics offers a broad portfolio of configurable specialty I/Os enabling flexible integration across multiple voltage domains and applications. Explore our specialty GPIO circuits and TSMC IP solutions. Additional variants and features can be supported upon request, allowing fast customization through minimal design changes. For more information, visit www.sofics.com or contact us at bd@sofics.com.