Tag: 5V0
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Sofics Datasheet – TSMC 40nm 5V GPIO
This specific IP macro is designed in 40nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS40N-5V-GPIO] Key Highlights Details Parameter Value VDD 1.1V ±10% VDDIO 5V ±10% Temperature Tj -40C to 105C Key Features Parameter Value Maximum bit rate…
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Sofics Datasheet – TSMC 22nm 5V0 GPIO
This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS22N-5V0-GPIO Key Highlights Details Parameter Value VDD 0.8V ± 10% VDDIO 5V ± 10% Temperature Tj -40°C to 105°C Key Features Parameter Value Maximum bit rate…
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Sofics Datasheet – TSMC 12nm 2V5 ESD Power Clamp
This TSMC 12nm 2.5V ESD Power Clamp IP macro provides compact, low-leakage ESD protection for FinFET designs. It is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-2V5-PC-ESD] Key Highlights Details Parameter Value VDD 2.5V ±10%…
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Sofics Datasheet – TSMC 12nm 1V8 ESD Power Clamp
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-1V8-PC-ESD] Key Highlights Details Parameter Value VDD 1.8V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 1.33A HBM ±2.1kV Leakage…
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Sofics Datasheet – TSMC 12nm 5V0 ESD Power Clamp
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-5V0-PC-ESD] Key Highlights Details Parameter Value VDD 5.0V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 3.0A HBM ±4.5kV CDM…