Tag: TSMC
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Sofics Datasheet – TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS65N-3V3-LC-LWC-RH-ESD] Key Highlights Details Parameter Value VDD 3.3V ±10% VDDIO VDD+0.3V ±10% Temperature Tj -55C to 125C Key Features Parameter Value TLP 1.33A…
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Sofics Datasheet – TSMC 22nm 5V5 ESD Power Clamp – Low Leakage
This TSMC 22nm 5.5V ESD Power Clamp provides low-leakage protection for sensitive supply and interface pins. The IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS22N-5V5-LL-ESD] Key Highlights Details Parameter Value VDD 5.5V…
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Sofics Datasheet – TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
This TSMC 5nm 1.8V, 1.2V and 0.9V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins. It is designed in TSMC 5nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS5N-1V8-1V2-0v9-LC-LWC01-ESD] Key Highlights Details Parameter…
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Sofics Datasheet – TSMC 22nm 5V0 GPIO
This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS22N-5V0-GPIO Key Highlights Details Parameter Value VDD 0.8V ± 10% VDDIO 5V ± 10% Temperature Tj -40°C to 105°C Key Features Parameter Value Maximum bit rate…
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Sofics Datasheet – TSMC 4nm 0V75 D2D AFE
This specific IP macro is designed in TSMC 4nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS4N-0V75-D2D-AFE Key Highlights Details Parameter Value VDD 0.75 V ±10% Temperature Tj -40 C to 105 C Key Features Parameter Value Rise time (10-90)1 <50 ps…
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Sofics Datasheet – TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-1V2-LC-ESD] Key Highlights Details…
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Sofics Datasheet – TSMC 3nm 3V3 ESD Local Clamp
This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-3V3-LC-ESD] Key Highlights Details Parameter…
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Sofics Datasheet – TSMC 3nm 3V3 GPIO
This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS3N-3V3GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 3.3V ±10% Temperature…
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Sofics Datasheet – TSMC 3nm 1V8 GPIO
This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS4N-1V8GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 1.8V ±10% Temperature…
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Sofics Datasheet – TSMC 2nm 1V2 GPIO
This TSMC 2nm 1.2V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS2N-1V2-GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 1.2V ±10% Temperature…