Tag: Local Clamp
-
Sofics Datasheet – TSMC 7nm 2V5 ESD Local Clamp
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. The 2.5V local clamp provides 1.33A TLP, 2kV HBM and 5A CDM performance with 10nA leakage at 25C. Its compact 1600µm² implementation supports local protection for…
-
Sofics Datasheet – TSMC 7nm 3V3 ESD Local Clamp
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. The 3.3V local clamp provides 2.35A TLP, 3.5kV HBM and 5A CDM performance with leakage below 50nA at 25C. Its compact 1800µm² implementation supports local protection…
-
Sofics Datasheet – TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Multiple clamp variants enable trade-offs between ESD robustness, parasitic capacitance, leakage and silicon area, including options down to 10fF capacitance and 133.84µm² area. Sofics Datasheet –…
-
Sofics Datasheet – SMIC 28nm 0V75 ESD Local Clamp – Low Capacitance
This specific IP macro is designed in 28nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-SMIC-28-0V75-LC-ESD] Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 0.75V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 1.33A HBM…
-
Sofics Datasheet – TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-1V2-LC-ESD] Key Highlights Details…
-
Sofics Datasheet – TSMC 3nm 3V3 ESD Local Clamp
This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-3V3-LC-ESD] Key Highlights Details Parameter…
-
Sofics Datasheet – TSMC 2nm 1V8 ESD Local Clamp – Low Leakage
This specific IP macro is designed in TSMC 2nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS2-1V8-LC-LL-ESD] Key Highlights Details Parameter Value VDD 1.8V ±10% IO signal voltage 1.8V ±10% Temperature Tj -40C to 125C Key Features Parameter Value…