Sofics Datasheet – TSMC 4nm 3V3 GPIO

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This specific IP macro is designed in TSMC 4nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

DS-TS4N-3V3-GPIO

Key Highlights

  • Broad portfolio of IO configurations from a single base architecture
  • Modular design enables fast and reliable turnaround and low NRE
  • Proven across multiple advanced nodes
  • Optimized for performance, power, and area trade-offs

Details

ParameterValue
VDD0.75V ±10%
VDDIO3.3V ±10%
Temperature Tj-40C to 125C

Key Features

ParameterValue
Maximum bit rate110Mbaud/s @ 5pF
Power consumption< 5uW
Drive strength5mA (other options available)
ESD robustness2kV HBM | 500V CDM

Area

TypeSize [μm²]
I/O8000 – 10000

Summary

Sofics specialty I/Os offer configurable GPIOs with multi-voltage support, over-voltage tolerance (OVT), and high-speed or ultra-low-power modes. Designed for advanced nodes, they enable reliable interfacing between low-voltage cores and higher-voltage or legacy systems.

An integrated voltage regulator ensures stable operation across wide voltage ranges, for auxiliary supply domains, supporting multi-voltage and OVT functionality without external components.

Pin Schematic

Features

  • Overvoltage tolerant design
  • Supports multiple supply voltages
  • Input enable/disable
  • Tri-state output
  • Pull select | Pullup/Pulldown
  • Compatible with TSMC I/O ring
  • Integrated voltage regulator
  • Other analog features such as I2C, I3C, SPI, UART, JTAG, PWM, WDT, slew rate control, fail-safe, drive strength options and more

Sofics offers a broad portfolio of configurable specialty I/Os and ESD protection enabling flexible integration across multiple voltage domains and applications. Additional variants and features can be supported upon request, allowing fast customization through minimal design changes. For more information, visit www.sofics.com or contact us at bd@sofics.com.

Sofics proprietary and confidential © 2026

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