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Radiation hard and cold-spare

Sofics has supported several companies in the past on radiation tolerant applications and other harsh environments. We worked both on prevention of Single Event Latch-up and on prevention of degradation due to Total dose irradiation.

Semiconductor devices that are used at high elevation or in space need special attention due to radiation. That counts for every digital or analog circuit including the I/Os and ESD protection cells.

Integrated Circuits can malfunction or get damaged under excessive radiation.

This is also relevant for semiconductor devices used in nuclear particle research (Cern) or nuclear facilities.

Contact us (info@sofics.com) to discuss your application.
Our solutions can meet rad-hard requirements.

Examples in different processes

Sofics ESD technology and knowledge used for rad-hard applications. We have provided our Analog IOs and ESD clamps to CERN for use in their experiments. They have sourced technology from us for 130nm, 65nm and 28nm CMOS technologies.

Typical GPIO libraries provide I/O circuits for 1.8V, 2.5V and 3.3V. Sofics developed analog I/Os for 1.0V and 1.2V interfaces for instance on 130nm, 65nm and 28nm. For those interfaces IC designers frequently connect thin oxide transistors directly to the pad so effective ESD protection is a must.

We have delivered ESD clamps to a US based FPGA maker that sources its solutions to aerospace applications. They ran tests (@ Berkeley) on our 65nm solutions and did not see failures up to 120 LET.

We have supported a few companies in their ASIC design for use in satellites. We have supported companies developing radiation hard products or libraries.

Lower leakage: Typical GPIO libraries use traditional ESD concepts like self-protective output drivers and BigFET rail clamps that introduce a lot of standby leakage. Sofics developed improved solutions that can reduce standby leakage by 100x or more.

Lower capacitance: While general purpose analog I/Os are suitable for most interfaces, high-speed communication (Wired, wireless or optical) needs a special solution. The traditional ESD concepts introduce a lot of parasitic capacitance. Sofics has created ESD protection with low-parasitic capacitance to enable higher data rates.

Any ESD robustness: Most of the GPIO libraries are designed for 2kV HBM ESD robustness. The Sofics proven methodology allows us to customize the on-ESD protection devices for any robustness level. Our engineers have provided custom cells beyond to 8kV HBM. Some customers asked us to integrate system level ESD robustness (IEC 61000-4-2 8kV) on the chip.

Higher voltage tolerance: IC designers sometimes need an interface that can tolerate a higher voltage level, beyond the maximum from the foundry GPIO library. Sofics engineers have designed 5V (and higher) solutions in most CMOS/FinFET processes.

Cold-spare Interface protection: Cold-spare relates to the fact that an unpowered (cold) replacement (spare) device is connected to a shared communication line. This is used a lot in space applications. System designers add an identical ‘cold spare’ device that can be used as a back-up when the first circuit is damaged somehow. If the primary circuit is not behaving correctly it can be turned down and the backup circuit is powered up to take over. The I/O voltage can be higher than its supply voltage. For ESD protection the diode from Pad to Vdd needs to be disabled.

These are examples from many IP delivery projects. If you did not find the example you were looking for you should Contact us (info@sofics.com) to discuss your application and requirements.
Our solutions can meet rad-hard requirements.

Testimonial: Renesas – Arquimea
  • Electronics for satellites
  • Cold spare interface protection
  • High ESD and higher immunity against radiation
Daniel González, head of microelectronics group

“You can’t afford failures in outer space.
We chose Sofics for access to the right expertise.
This reduces risk and saves time and money.”

Further reading