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Advanced CMOS (40nm to 22nm)

Transistors in advanced CMOS processes are very sensitive to ESD stress. Additionally, the conventional ESD approaches are no longer effective.

Moreover, the foundry provided General Purpose I/O libraries introduce contraints. The parasitic capacitance of the integrated ESD protection clamps is too high for interfaces running at speeds beyond 10 Gbps. The leakage current of traditional ESD clamps prevents low-power applications. The I/Os are typically designed for 2kV HBM while many aaplications require more ESD robustness

Sofics IP for advanced CMOS technology

TSMC 22nm
TSMC 28nm
TSMC 40nm
UMC 28nm
SMIC 40nm
Proprietary IDM fab on 40nm

High-speed interfaces
Beyond standard voltage levels

Sofics IP is used in high bandwidth communication interfaces for wired and optical networks including 28Gbps, 56Gbps SerDes. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

Our IP was used for sensor interfaces, battery connections and more. We have delivered solutions for high voltage tolerance (5V or higher) and also protected interfaces based on thin oxide transistors (1V and lower) thanks to a flexible but deterministic solution set.

Battery powered applications
Harsh environments

Customers have integrated Sofics ESD in IoT systems. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles. Sofics has solutions available for interfaces and rail clamps.

Automotive applications typically require higher ESD robustness levels. Sofics ESD technology can be easily scaled to reach higher HBM and CDM protection levels. In some cases the on-chip ESD cells are adapted to sustain contact discharge 8kV IEC 61000-4-2.

Our customers have created amazing products. Examples include high-speed interfaces for datacenter chips (wired and optical), Artificial Intelligence (AI) processors but also for low-power Internet of Things devices.

Further reading

Blog article “Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration
Blog article “Optical communication also requires ESD protection
Press release about our cooperation with Nvidia and ICsense