Why IC designers need custom ESD cells
SOI technology introduces several challenges for the ESD designer. Circuits on advanced SOI CMOS processes are very sensitive to ESD stress. The thin oxide transistors can fail at transient voltage of 5V or less.
The shallow junctions in thin film SOI processes strongly reduce the intrinsic failure current of basic ESD devices. The conventional ESD approaches are much less effective
Sofics IP for SOI technology
Process technology covered
IDM fabs 130nm
IDM fab 90nm
IDM fab 65nm
Key focus areas
Beyond standard voltage levels
Sofics IP is used in high bandwidth communication interfaces networks. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.
Our IP was used for sensor interfaces, battery connections and more. We have delivered solutions for high voltage tolerance (5V or higher) thanks to a flexible but deterministic solution set.
Battery powered applications
Customers have integrated Sofics ESD in IoT systems. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles. Sofics has solutions available for interfaces and rail clamps.
Some applications require higher ESD robustness levels. Sofics ESD technology can be easily scaled to reach higher HBM and CDM protection levels.
IC products from our customers
Our customers have designed different types of products on SOI technology. Examples include wireless LNAs, PAs, high-performance compute, wireless IoT, bluetooth, wifi circuits, low-power Internet of Things devices.