Tag: Datasheet
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Sofics Datasheet – TSMC 3nm 3V3 ESD Local Clamp
This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS3N-3V3-LC-ESD] Key Highlights Details Parameter…
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Sofics Datasheet – TSMC 3nm 3V3 GPIO
This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS3N-3V3GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 3.3V ±10% Temperature…
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Sofics Datasheet – TSMC 3nm 1V8 GPIO
This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS4N-1V8GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 1.8V ±10% Temperature…
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Sofics Datasheet – TSMC 2nm 1V2 GPIO
This TSMC 2nm 1.2V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS2N-1V2-GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 1.2V ±10% Temperature…
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Sofics Datasheet – TSMC 2nm 1V8 GPIO
This TSMC 2nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS2N-1V8-GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 1.8V ±5% Temperature…
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Sofics Datasheet – TSMC 12nm 0V8 ESD Local Protection Low Cap
This TSMC 12nm 0.8V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins. It is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-0V8-LC-LWC01-ESD] Key Highlights Details Parameter Value VDD 0.8V…
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Sofics Datasheet – TSMC 12nm 2V5 ESD Power Clamp
This TSMC 12nm 2.5V ESD Power Clamp IP macro provides compact, low-leakage ESD protection for FinFET designs. It is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-2V5-PC-ESD] Key Highlights Details Parameter Value VDD 2.5V ±10%…
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Sofics Datasheet – TSMC 12nm 1V8 ESD Power Clamp
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-1V8-PC-ESD] Key Highlights Details Parameter Value VDD 1.8V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 1.33A HBM ±2.1kV Leakage…
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Sofics Datasheet – TSMC 12nm 5V0 ESD Power Clamp
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Sofics Datasheet – [DS-TS12N-5V0-PC-ESD] Key Highlights Details Parameter Value VDD 5.0V ±10% Temperature Tj -40C to 125C Key Features Parameter Value TLP 3.0A HBM ±4.5kV CDM…
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Sofics Datasheet – TSMC 4nm 3V3 GPIO
This specific IP macro is designed in TSMC 4nm and can be ported to other technologies upon request using Sofics in-house design tool flow. DS-TS4N-3V3-GPIO Key Highlights Details Parameter Value VDD 0.75V ±10% VDDIO 3.3V ±10% Temperature Tj -40C to 125C Key Features Parameter Value Maximum bit rate 110Mbaud/s @…