Time to say farewell to the snapback ggNMOS for ESD protection

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RIP ggNMOS ESD clamp – thanks for years of dedication and service

The snapback ggNMOS has been our superhero ESD device for years. With the right analysis, understanding and some tricks, ESD engineers worldwide relied on it and gained respect from their peers. Engineers could impress their colleagues who believed it was pure magic. The ggNMOS was our rock and source of strength.

However, in more recent years, ggNMOS had difficulties to follow and adapt to all the newest innovations and process scaling. We could still rely on it for special cases but it became clear the end was near.

With its passing, the ggNMOS leaves behind a legacy of robust IC products.

IC engineers that design ESD protection clamps for chips in mature low voltage (5V or lower) CMOS technologies (0.18um or older), are spoiled. In those processes, ESD diodes can conduct a lot of ESD current, typical ESD design windows are very wide and the NMOS transistor is a perfect ESD protection clamp for most stress combinations.

Snapback NMOS based ESD protection

In those mature process nodes, the NMOS transistor combines several good characteristics during ESD events

  • Snapback operation when the parasitic NPN bipolar transistor is activated.
  • A small device is sufficient for standard ESD robustness (It2) due to strong NPN performance.
  • Effective protection for most functional circuits thanks to a low trigger voltage (Vt1), defined by the Drain-Substrate junction breakdown, below the typical failure voltage of the gate oxide and core circuits.
  • Low latch-up risk because the clamping/holding voltage (Vh), defined by the NPN beta, is above the supply voltage.
Basic IV curve for an ESD clamp device. The clamp has a trigger voltage (Vt1), a clamping/holding voltage (Vh), an on-resistance (Ron) and a failure current level (It2).

Thanks to these characteristics, the NMOS transistor is used as ESD clamp in various locations in the chip in mature processes.

  • The ggNMOS can be used as a power clamp device
  • Designers use the device also as local protection for input gate protection
  • The output drivers can be easily made self-protective
  • A small ggNMOS, behind an isolation resistance is a perfect CDM clamp
  • The secondary protection approach can be used to extend the ESD design window for more sensitive circuits
CMOS inverter style output driver. Self-protective output approach.

“The grounded-gate NMOST (ggNMOST) is
one of the workhorses in the field of ESD”

Theo Smedes, Fellow for ESD, Latch-up and EOS within NXP Semiconductorslink.

Continuously updated and improved

Because it is such a nice, universal approach, many ESD and fab process engineers worldwide have come up with tricks to maximize the usability whenever process changes were made. Numerous publications provide details about adding a dummy fingers, nLDD blocking masks, silicide blocking, back-end-ballasting, multi-finger triggering techniques and ESD implant masks.

Snapback behavior of a (thick oxide) NMOS transistor in a 180nm CMOS process.

Unfortunately all good stories end someday. Based on the good experience in mature nodes, engineers wondered if the snapback NMOS can also be used in more advanced CMOS, FinFET, high voltage, BCD or SOI processes. Foundries have promoted the use of the snapback NMOS transistor for ESD protection in each of those processes but that has caused a lot of product failures.

Advanced CMOS technology

For instance, in more advanced process technology, it is not at all gloomy. There are a number of trends that play a role in the demise of the ggNMOS based ESD protection for the most sensitive interfaces.

Scaling transistors and following Moore’s law have served the industry well for more than 50 years in providing integrated circuits that are denser, cheaper, higher performance, and lower power. – “CMOS Scaling Trends and Beyond”, https://www.computer.org/csdl/magazine/mi/2017/06/mmi2017060020/13rRUwI5TUw
  • Junctions became shallower and dimensions smaller in each consecutive process node. This reduced volume caused a drop in robustness of the parasitic NPN device. From more than 10mA/um in 0.25um the performance dropped to less than half in 28nm CMOS. Thus, for the same ESD robustness the perimeter needs to be doubled.
  • The Vt1 trigger voltage dropped at each node from ~6V in 180nm to ~4V in 28nm CMOS. However, the breakdown voltage of the thin gate oxide dropped faster (>8V to less than 3.5V). From the 90nm node on, the drain-substrate breakdown voltage is roughly the same as the (thin) oxide breakdown voltage. This means that e.g. a 40nm ggNMOS ESD clamp cannot protect a thin oxide interface anymore, let alone itself.
  • ESD engineers came up with clever techniques to reduce the trigger voltage down to the holding voltage with e.g. bulk or body or gate bias. This postponed the problem.
  • The clamping voltage is also reduced at more advanced CMOS nodes (>4V to 3.5V) but the decrease is slower. In the 28nm node the clamping voltage is higher than the thin oxide breakdown voltage. The end…
ESD relevant trend lines for CMOS scaling. The Vdd voltage (blue line) has been reduced in every node. The thin oxide breakdown voltage (red trend line and red rectangles) is reduced due to the use of thinner oxides. The green trend lines and circles depict the Vt1 trigger voltage (solid line) of a thin oxide ggNMOS device while the dashed green light is the trend line for the Vh clamping voltage. One can clearly see the reduced margin and lack of effective protection from 90nm.

People have successfully used ggNMOS clamps in 28nm CMOS for instance as CDM (secondary) clamps. Thanks to the short pulse duration the transient gate oxide breakdown is a bit higher. For the main or primary ESD protection it is better to rely on other ESD protection concepts. For interfaces based on thick oxide transistors the ESD design window is still large enough. Most general purpose I/O cells are based on thick oxide transistors.

FinFET technology

Similar to advanced CMOS, the snapback NMOS approach is no longer the preferred option in FinFET processes. Frequently the NMOS transistor does not survive snapback operation for 100ns TLP pulses, even with silicide blocked drains. The FinFET NMOS transistor fails to protect itself during ESD stress. The (thin) gate oxide breakdown is further reduced to 3V or less.

The ESD design window (for thin oxide interfaces) is further reduced in FinFET technology. The snapback ggNMOS transistor is no longer effective.

Even interfaces based on thick oxide transistors are in trouble. Frequently thick oxide NMOS FinFET transistors fail at snapback too. Fortunately other protection devices can be used. Find out more in our other blog article (ESD protection for FinFET).

High voltage and BCD processes

In high voltage and BCD processes designers should certainly look for alternatives. Major foundries are (still) promoting NLDMOS transistors for ESD protection as power clamp, self-protective drivers and local I/O protection. Of course, IC designers creating complex analog circuits frequently rely on those foundry guidelines and recommendations.

TLP measurement of a high voltage NLDMOS device. Notice the trigger voltage of of 70V (Vt1), clamping voltage of about 10V (Vh) and failure current of almost 2A and low resistance,

However, this recommendation leads to reduced yield, field failures, delayed product introductions and a lot of grey hair. The only good that comes from these foundry recommendations is more debug/consulting business for Sofics. We frequently meet IC designers that followed the foundry recommendation but subsequently run into ESD or latch-up issues. They reach out and expect a quick-fix solution within 2 weeks for their next product re-spin.

But debugging product ESD failures is not our passion. Our engineers prefer tackling ESD challenges pro-actively. On every test chip opportunity they look for improved protection concepts that nobody has tried before. We invent, develop and optimize ESD protection solutions that can be reused by many, without the need for a product re-spin.

Who is right?

So what is going on? Who is right? The foundry ESD experts have tested their proposed ESD protection clamps and eagerly share the TLP, HBM analysis to demonstrate that the NLDMOS based ESD protection clamp can be trusted.

On the other hand, Sofics has been able to characterize the ESD properties of NLDMOS transistors in many BCD processes from different foundries and proprietary fabs. Our conclusion is that IC designers should refrain from using snapback NLDMOS transistors for ESD protection.

Test-driven development

In the software world developers use “test driven development”. They first define all the tests conditions and constraints that the new software module must be able to pass. They first create a test procedure before they start coding the function.

In our quest for novel protection concepts we have used a similar approach. Based on our experience working with many customers and process technologies we define the minimum conditions ESD clamps must meet.

Degradation after repeated ESD stress?

Surely, when an ESD clamp is tested at the foundry and passes 2kV HBM or the TLP analysis shows a nice snapback behavior (example above) and the leakage current remains below the 1uA level up to 1.3A it should be OK, right? It depends. A single test condition is not enough.

One of the test conditions we strongly believe in is “lack of degradation”. We recommend using ESD protection devices that do not degrade after repeated (low current) ESD stress pulses. Back in 2001, such no-degradation test condition was actually proposed in a peer-reviewed publication from Imec in Belgium (reference).

Suppose a clamp is designed for 2kV HBM, roughly 1.3A peak current. When that clamp is stressed 1000 times at, let’s say, 1A (~1.5kV HBM) it should behave exactly the same as for the first pulse.

Whenever we run this test on high voltage NLDMOS transistors we notice a shift in leakage. Every time the device is triggered into snapback some charges are trapped in the oxide close to the NMOS channel. The trapped charge influences the device behavior.

HV NLDMOS devices were stressed with multiple (<50) pulses at different current levels to investigate the degradation. Above the NPN turn-on the degradation is visible in the increase in leakage current.
Charge trapping in the Field Oxide at the bird’s beak reduces the breakdown voltage locally, represented by the black spot at the drain. Due to the reduced breakdown voltage the following ESD stress current (2,3) will be localized at the black spot, preventing uniform conduction through the whole finger.

Sometimes the leakage shift is even visible during a standard TLP test. Changing the number of steps can influence the failure current. The figure below shows a gradually increasing leakage current for increasing TLP stress levels. Moreover, it shows that the leakage increases faster if the TLP pulse density is higher.

2 identical high voltage ggNMOS devices on the same (test chip) wafer. The IV characteristic is the same with Vt1 above 70V and holding voltage of about 10V. The failure current is different though. The blue measurement shows a failure around 700mA. The red measurement shows a failure at 1.3A, nearly double. The only difference between both measurements is the pulse density.

In the 2004 Sofics paper on ESD clamps for high voltage processes more data is shared specifically for NLDMOS devices (link). The article also includes further background on what is happening inside the device.

Other problems

There are other issues with snapback NLDMOS for ESD protection. There is a large difference between the Vt1 trigger voltage and the Vh clamping voltage. This can lead to non-uniform triggering, between different device fingers and even within a single device finger.

Non-uniform conduction of ESD current demonstrated for different HV-ggNMOS transistors

The trigger voltage (Vt1) is high but typically the clamping/holding voltage is rather low (10V or lower). This could lead to latch-up issues when the NPN is triggered under powered conditions. It is better to rely on ESD protection clamps with a clamping voltage above the signal/power voltage. Sofics has developed a broad range of such devices for high voltage processes since 2008. They are available under the PowerQubic brand.

Another typical issue is a so-called window effect. The device survives high (2kV HBM) ESD stress but fails at a low (e.g. 500V HBM) level. This behavior can sometimes be checked with TLP tests with different rise times. When ggNMOS devices are stressed with different rise times the behavior is different. For fast rise times, the bulk (and gate) voltage can be raised, lowering the Vt1 trigger voltage.

Influence of the pulse rise time on ggNMOS. (left side) A fast ESD pulse can couple the bulk of the NMOS to a higher potential for a short period, reducing the trigger voltage. (right side) A clear Vt1 reduction is visible, while the remaining part of the IV curve remains the same.


For years we have relied on the snapback ggNMOS device. It has been the perfect ESD device with great intrinsic properties and ways to optimize for more demanding applications. Unfortunately in advanced technology like 28nm CMOS, FinFET processes and certainly for high voltage processes the device needs to be replaced with alternative ESD protection concepts.

Reach out to us if you want to discuss your ESD protection strategy. As discussed, we prefer to look at it before the tape out and rely on silicon proven and tested IP blocks.

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