Category: ESD protection approaches
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ESD basic: Silicon Control Rectifier (SCR)
SCR intro: Silicon-controlled rectifiers (SCRs) are interesting devices that can be used for on-chip ESD protection, if (and only if) they are properly designed and biased. SCRs are used for high-speed/RF or low-capacitance, small area/high-performance ESD solutions in all CMOS technologies, including SOI and FinFET (down to 3nm today). SCR…
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ggNMOS (grounded-gated NMOS)
ggNMOS intro: For decades, a traditional workhorse device for ESD protection for standard applications in CMOS technology has been the grounded-gate NMOS device (ggNMOS). Nevertheless, we have been explaining the operation of this device countless times, including as recently as 3 weeks ago. So, it is time for a short…
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3 approaches to handle EOS ‘requirements’
EOS, or Electrical Overstress, is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product. It is important to discuss because many products are damaged this way. This article includes case studies and 3 approaches to handle those requests.
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Optimized on-chip ESD protection to enable high-speed Ethernet in cars.
In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution. With its local ESD clamp approach,…
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Selecting custom ESD IP for your next IC
Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps. Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event…
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Introduction: ESD protection concepts for I/Os
There are many different approaches to ensure effective ESD protection for integrated circuits. It is important to select the right approach for each interface and power domain. This article outlines the main options for Interface protection.
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Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes
Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions. We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
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Time to say farewell to the snapback ggNMOS for ESD protection
For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below). However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.
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ESD protection solutions for space applications
Space applications require custom I/O and ESD protection solutions. Sofics proprietary ESD technology has been used for a number of aerospace projects. Our engineers delivered custom rad-hard ESD devices for TSMC 28nm, 65nm and 130nm CMOS technologies. The cells enable low power design in an extended temperature range. Different concepts…
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Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration
Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher…